Purpose/Goal

Computer instructions and instruction sequences date back to Babbage's Analytical Engine. The electronic equivalent, the von Neumann architecture, goes back eighty years. Is it time for a change?

The purpose of this project is to explore "reconfigurable computing", an alternative to the von Neumann architecture. Reconfigurable computing attempts to implement application logic directly in hardware using state machines which operate in parallel.

State machines do not have objects, subroutines, for loops, or if statements. Since state machines running on an FPGA can update all state machines at once, older serial oriented languages like C and Python are poor choices for programming a reconfigurable computer. A new programming paradigm is needed.

The Spreadsheet State Machines project attempts to use a spreadsheet as a general purpose, high-level programming language for an FPGA based reconfigurable computer. Coding and debug of the application is done in the spreadsheet. The application can be exported as Python, C, or OpenCL for faster execution, or as Verilog to run on an FPGA.

A spreadsheet is the only popular programming paradigm in which all variables in the program (i.e. cells) update at once. This makes a spreadsheet a good design paradigm for FPGA designs in which all circuit variables (i.e. registers) update at once. One advantage of a spreadsheet is that it is not a new programming paradigm. Hopefully this will make it easier for non-engineers to write applications.

Programming in spreadsheets will certainly be challenging. Consider the facilities available to current high-level languages versus the facilities available to a spreadsheet.

C/C++:
    Assignment    Structures    Data types    Objects
    If-then-else  For loops     Subroutines   Inheritance 
    Libraries     File I/O      Malloc        OS support
Spreadsheets:
    Assignment

In theory, all computer programs are event-driven state machines, and, in theory, any event-driven state machine can be modeled in a spreadsheet. In theory. We hope to see if, in practice, it is possible to build high level applications in a spreadsheet and export them to Verilog.

Perhaps some day a spreadsheet might be able to hide the details of Verilog and FPGAs in much the same way that a C/C++ compiler hides the details of assembly language and the host machine architecture.